1. Field of the Invention
The present invention generally pertains to design of ICs containing large power transistors for low loss switching applications. In particular, power cells are designed to achieve low values of on-resistance (RDSon).
2. Related Art
Successful IC (integrated circuit) development for medium, high power, and very high power applications requires power transistors or cells that achieve very low values RDSon. IC applications including but not limited to power conversion, class-D audio amplifiers, power control for PC products, automotive, MEMS and display drivers leverage low RDSon to improve key figures of merit including energy efficiency, switching and conduction power loss, thermal problems, and switching frequency. The voltage levels of the transistors involved typically range from values of 5V to greater than 700V. The RDSon values required can reach into the sub 100 milli-ohm ranges.
In general, the RDSon of a transistor is inversely proportional to the conducting area of a power transistor. The translation into actual design parameters depends on the transistor type. For example, in a Field Effect Transistor, the gate width design parameter increases or decreases the conducting area. The gate width can be given by a product of design parameters such as the width of a single gate and the number of gates placed in parallel. Ultimately, increasing the total gate width decreases the RDSon. Clearly, increasing gate width comes at the expense of increased area consumed by a power transistor in an IC, ultimately increasing the size of the IC. The cost to fabricate an IC is directly proportional to the size of an IC. Therefore, designing power cells to achieve an RDSon design specification in the smallest area possible is an important factor in reducing IC fabrication costs.
A complicating factor in power cell design is the metal routing or interconnect that provides access to and networks the intrinsic transistors. The total RDSon of a power cell contains resistance contributions from the intrinsic transistor (Rint) and the metal interconnects (Rmetal). As previously stated, the total RDSon of a cell decreases as the gate width and, hence, device area increases. Typically, the intrinsic transistor resistance Rint decreases as the device area increases. By contrast, as the cell area increases, the metal interconnects resistance Rmetal increases. The resistance of a metal interconnect generally is proportional to the length of the metal interconnect, Lmetal, which in turn is proportional to the device area. Therefore, the resistance of the metal interconnects, Rmetal, increases as the device area increases. Equations (1) through (3) provide a high level analytical description of RDSon as a function of cell area.RDSon=Rint+Rmetal  (1)Rint∝1/Area  (2)Rmetal∝Lmetal∝Area  (3)
Clearly, the two components of RDSon possess generally reciprocal properties, in other words, an increase in cell area tends to increase Rmetal while decreasing Rint. When the goal is to minimize RDSon, this circumstance leads to striking a balance between Rint and Rmetal, a non-monotonic problem.
In general, the minimum value for RDSon can be modeled as a global minimum in a multivariate, nonlinear space. However, previously, multivariate nonlinear optimization of parameters, intending to produce a target value for a predetermined figure of merit, has been avoided in favor of more simplistic “tweaks,” which may involve numerous iterations from design through fabrication, and which still may not achieve a satisfactory outcome. For example, in the past, much effort has been focused on lowering the impact of Rmetal on RDSon, for example, by determining advantages metal interconnect styles, which may encompass physical, geometrical and connection properties.
Simulation models, for example, SPICE models, have been created to account for the resistance contributions from the intrinsic transistor (Rint) and the metal interconnects (Rmetal). These models typically calculate metal resistance contributions by implementing simple device formulations based on lumped calculation of metal resistance from a variety of geometrical input parameters and, usually, uniform sheet resistivities p.
Typically, a designer manually chooses geometric layout parameters with limited to no guidance on the inherent layout parameter effects on device performance, for example, as measured by figure of merit, an RDSon-Area product. At present, most power cell design methodologies are based on the cause and effect design or, in some instances, feed forward design, where power device geometrical parameters being determined iteratively to produce a target silicon-characterized RDSon specification within a selected set of constraints.
Also, some optimization methodologies employ massive look-up tables having an exhaustive set of pre-calculated “optimized parameters.” These look-up tables typically are derived by brute force optimization analyses for permutations of device geometries, design rules, device power capability, parasitic or intrinsic resistance, capacitance, or inductance, and an array of other device parameters and Figures of Merit (FOM). While an impressive feat, such data sets tend to use significant economic, personnel, training, and infrastructure resources to develop, to maintain, and to update and adapt. A comprehensive optimization look-up table also tends to be cumbersome and inherently inertial, reducing a design team's ability to meet the rapidly changing requirements and short product cycles.
Moreover, a look-up table is a quantized, open-form solution using a collection of data points which, by their nature, are applied as an approximation to an actual target value, unless the data truly coincides with the actual target value. When applied to a problem seeking a global minimum, a look-up table may not find the true minimum. As the number of parameters and ranges of parameters in dimension and scope, there is a greater likelihood of a quantization error-type of imprecision of the data, which lead away from the global minimum.
Overall, these methodologies contain shortcomings that can lead to overdesign, increased costs, and longer design times. In an example of overdesign, an IC designer may attempt to compensate for potential methodology inaccuracies by increasing the device design area, resulting in a power device that consumes unnecessary area and hence increased IC cost. Because of these inaccuracies, real or perceived, an IC designer may spend additional design time to use brute-force design iterations, and to analyze the results from each of the corresponding intermediate silicon iterations. Increased design time may carry heavy penalties, including higher development resource costs. Further, increased silicon iterations can translate into increased silicon costs, increased testing costs, and increased human resource costs. Perhaps the heaviest burden of increased design time or silicon iterations is loss of market share due to delay in time to market, and higher product costs.
Quite often, optimization of power MOSFET parameters is closer to an art, relying on empirically-derived techniques, simplistic models, rules of thumb, corporate tribal knowledge, design methodology preferences, vendor suggestions, or ad hoc trade-offs, which are applied iteratively and, frequently, after fabrication of wafers including power MOSFET-bearing devices. The artful optimization of power MOSFETs may not timely realize optimization targets and may be limited due to pragmatic considerations, including development costs and fabrication facility availability. There is a need for an elegant, compact, closed-ended analytical method and apparatus capable of identifying an optimum value for a target parameter, and of manipulating other parameters having influence the target parameter to produce a device configuration capable of efficiently realizing, in functional silicon, the optimum value for a target parameter.